A double level conductive structure is provided wherein one conductor layer permits impurities to pass therethrough in a given impurity introduction step while double conductor level portion substantially prevents such impurities from passing therethrough due to a greater combined resistance to impurity penetration.
Several problems persist in the semiconductor industry and more Particularly in CMOS products and their manufacture. Common to existing CMOS processes are the need for a reduction in the NMOS to PMOS spacing and the need to reduce body overlap of the MOS source/drain. It is additionally necessary to find methods of reducing the source and drain capacitance and resistance in CMOS devices. Furthermore, it is necessary to reduce the threat of contact punch through of the source and drain regions.
Typical approaches to solving these problems have included the provision of guard rings between the source and drain regions of adjacent devices, the use of self-aligned gate processes, the careful tailoring of source and drain doping levels and the provision of thin (or not so thin) gate oxides. Notwithstanding these approaches it is a continuing objective in the semiconductor processing field to obtain further improvements in each of the above-identified areas.
It has been discovered that by providing a buried dielectric beneath the sources and/or the drains of adjacent CMOS devices which are abutted for instance drain to drain, it is possible to provide a conductive layer providing an ohmic contact to each of the adjacent regions thereby allowing zero spacing between adjacent NMOS and PMOS devices. This approach is described in greater detail in the co-pending, and commonly owned application of Kenneth K. O., Lawrence G. Pearce and Dyer A. Matlock entitled "CMOS Device Having Reduced Spacing Between N and P Channel Transistor Pair", filed May 29, 1987, U.S. Ser. No. 055,558 now U.S. Pat. No. 4,829,359. A feature of this approach is the utilization of a powerful ion implanter capable of forming a buried dielectric region. The problems of reduced NMOS to PMOS spacing are solved with this approach since the NMOS and PMOS drains are shorted by the conductor thus allowing them to abut without breakdown problems. In ordinary CMOS circuits the drain must be contained within the body in order to prevent breakdown or MOS action between the drain of one type device to the body of the adjacent device of the opposite type. The use of the buried dielectric solves this problem.
An alternative process has been discovered and is described herein which creates a buried oxide region. One manner of implementing this process permits formation of the buried oxide without the use of ion implantation to directly form this buried oxide region. Thus, the powerful ion implanter of the above-mentioned process is not needed in the present approach.
As used herein, the term sidewall isolated refers to any semiconductor region laterally bounded by a dielectric material. As shown in a preferred embodiment of FIG. 4a, a single crystalline substrate 400 is provided with a pattern of dielectric sidewall isolating regions 420. These regions may be formed by, for instance, local oxidation of the substrate or high energy implantation of impurities or by etching the silicon in the isolation regions, forming a dielectric and planarizing the surface, it being significant that the sidewall isolated structure formed in the substrate extend from the substrate surface 401 substantially into the substrate and it being preferred that the top surface 421 of the dielectric regions 420 be substantially planar with the top surface 401 of the substrate. In a silicon substrate 400, an oxide region 420 may be formed by a local oxidation process. The local oxidation process uses a thin oxide region to protect the silicon surface, silicon nitride is deposited and patterned to remove nitride from areas which are to be oxidized, silicon will only be oxidized in the exposed areas, the silicon nitride protected areas will not oxidize; the wafers are oxidized to the desired depth and the nitride is removed. The surface may then be planarized either by removal of that portion of oxide which is above the surface 401 of the silicon substrate or by building up the single crystalline silicon to a new level 401 which above the original substrate surface such that the silicon and oxide have a planar top surface 401. The planar surface facilitates subsequent processing.
Another method of forming the sidewall isolating regions may be by implanting oxygen to the proper depth, then raising the temperature to convert the implanted oxygen to silicon dioxide. This process minimizes the temperature time product required to form the isolation region and also minimize the lateral encroachment into the single crystal region by the isolation region. In a local oxidation process as oxygen is diffusing downward some is also diffusing laterally causing encroachment into the single crystal region.
A planarized trench oxide isolation is performed by etching the silicon in the trench isolation regions to the desired width and depth, depositing the insulating oxide sufficient to completely fill the trench isolation region and also cover the surface of the wafer, a planarization process such as described in U.S. Pat. No. 4,515,652 is used to remove the oxide from the surface of the wafer and leave the oxide in the trench approximately at the same level as the surface of the wafer.
The process of the present invention commences with the formation of a sidewall isolated wafer consisting of an N+ substrate having an N-single crystalline layer thereover and having oxide isolating tracks in the surface of the wafer to define isolated regions within the wafer. An epitaxial process is used to form a single crystal layer over the single crystalline regions of the wafer and to form polycrystalline silicon over the oxide regions of the wafer. This wafer is then used in a sidewall isolated CMOS process. The device is aligned to the single crystal regions such that the gate regions are over single crystal regions and NMOS and PMOS drain extensions are built over the original buried oxide regions. The NMOS and PMOS drains may abut the buried oxide regions.
A second manner of implementing the process involves providing a side wall isolated wafer, implanting bodies, growing a gate oxide and forming a gate polycrystalline silicon which is oversized, then removing the exposed gate oxide, depositing a second polycrystalline silicon layer and patterning, using a photoresist process, to provide openings for implanting source and drain regions. The source and drain regions are then implanted.
A third alternative process involves providing a sidewall isolated wafer, implanting bodies and growing a gate oxide, patterning the gate oxide followed by depositing a polycrystalline silicon layer and patterning the polycrystalline silicon layer over the gate oxide. The process is then concluded as described with respect to the second process alternative described above.
The fourth alternative implementation of the process of the invention involves commencing with a sidewall isolated wafer, implanting device bodies, growing a gate oxide and depositing a polycrystalline silicon layer over the oxide and defining the polycrystalline silicon layer. Next are implants of N and P LDD (lightly doped drain) regions followed by the formation of gate sidewall spacers. A mask layer protecting the gate and gate spacers is provided and the spacer on the polycrystalline silicon region which will become an extension of the source/drain region is removed. The photoresist is stripped and the exposed gate oxide is then removed. The N+ regions are protected with photoresist and a P+ implant is provided on the P type regions. The P type regions are then protected and the N+ implants are provided to form the sources and drains. The gate polycrystalline silicon is doped by the source/drain implants. A silicide is then formed on all exposed single crystal and polycrystalline silicon regions. It is noted, however, that the silicide metal will bridge the gate oxide (approximately 250 angstroms) but will not bridge the gate spacer oxide (approximately 5000 angstroms). Next an oxide is deposited, the contacts are cut, metal is deposited and patterned, additional oxide is added, vias are formed and final metal is applied. A passivation layer is then applied and bond pads are opened for final bonding. It is noted that all contacts in this arrangement are to the polycrystalline silicon regions as opposed to any single crystal regions thus permitting all contacts to be made at the same level. It is further noted that this arrangement could be modified such that some contacts are made to the underlying single crystal regions in order to reduce source/drain area required.
It is noted that several variations of each of the above process approaches are possible. Such as, formation of the sidewall isolated wafer by either a local oxidation or a planarized oxide process; formation of transistors employing a lightly doped drain if a minimization of hot electron effects is desired., transistors can be formed without lightly doped drains; the gate can be doped when the source and drains are doped or by a separate polycrystalline silicon doping operation; starting wafers can be of either N or P doped silicon or of epitaxially grown silicon on either N+ or P+ substrates or silicon on insulator substrates or dielectrically isolated substrates; the bodies can be either single well or twin well; the sequence for implanting or diffusing N and P type impurities can be reversed; one or more levels of metal can be employed on either a planar or nonplanar oxide; alternative dielectrics can be used including oxide, nitride or oxynitride; either a photoresist or metal could be used to block implants; the use of polycrystalline silicon to form the source and drain regions could be applicable to NMOS and PMOS processes as well as to CMOS processes; prior to depositing the metal which will be converted to a silicide a portion of the exposed gate oxide over source/drain regions could be masked to allow only the unmasked portions of the source/drain regions to be silicided; the silicide could be formed prior to the doping of the source and drain regions; and any number of different materials could be used to form the silicide including Ti, W, Cr, Mo, Ta, Pt, Pd, Co or other silicide forming metal. Another alternative is the use of a selective deposition of a low resistivity material such as Ti, W, Cr, Mo, Ta, Pt, Pd, Co or other metals without converting these materials to a silicide.
It is additionally noted that a selective epitaxial growth prior to the silicide formation in the fourth implementation of the process described above would provide the necessary silicon for the silicide without requiring consumption of any of the existing silicon which might otherwise cause a shorting of the source/drain region to the body by the silicide. The selective epitaxial growth could be designed so as not to deposit on the oxide, especially the gate spacer oxide.